1. Field of the Invention
The present invention relates to display device controllers. In particular, the present invention relates to a video controller with a read buffer for reducing the time required for a central processing unit to read the memory of the video controller.
2. Description of Related Art
Many present day computer display systems often include a video controller 20 coupled between a central processing unit (CPU) 10 and a display device 16. The video controller 20 stores data representing the images to be displayed. FIG. 1 illustrates the conventional video controller 20 including a video memory 12, a video display control unit (VDCU) 14 and a video processing device 18. The CPU 10 transmits data and control signals to video memory 12 and refreshes the information stored in video memory 12. Aside from other control functions, the VDCU 14 periodically causes the video memory 12 to send data to the video processing device 18. The video processing device 18 then strings the data in a line and transmits it to display device 16. Using this method, the information on display device 16 is periodically refreshed.
As shown in FIG. 1, a typical video system allows either CPU 10 or VDCU 14 to utilize memory 12 at any particular instant. Therefore, it is necessary to allocate times for CPU 10 and VDCU 14 to utilize memory 12. Otherwise, both devices 10, 14 may attempt to use memory 12 simultaneously which causes unpredictable results. The typical method for allocating time periods to access memory 12 usually divides the CPU cycle into time frames for each device 10, 14 to use memory 12. Under such an allocation scheme, CPU 10 can only utilize memory 12 between t1 and t3, and between t5 and t6, as shown in FIG. 2. The periods between t3 and t5 and between t6 and t7 are allocated for use of memory 12 by VDCU 14. However, the prior art CPU cycle allocation method causes system delays. As shown in FIG. 2, no delay is caused by the allocation scheme as long as the memory write (MEMW) signal is pulled low near the beginning of time frame allocated for use by CPU 10 as shown in waveform B. If the memory write (MEMW) signal is pulled low after more than half the allocated time frame has elapsed (e.g., between t2 to t3), then CPU 10 must wait until the next CPU slot for access to memory 12, as shown in waveforms C and D. Having to wait for the next available CPU slot causes considerable delay in processing.
The prior art has added a write buffer 22 to reduce the effects of the aforementioned system processing delay. For example, U.S. patent application Ser. No. 07/602,479 discloses a video controller with write buffer 22 to store the control and data signals sent by CPU 10, and send these signals to video memory 12 during the next time slot allocated to CPU 10. Write buffer 22 greatly improves the efficiency of writing to video memory 12 as well as the efficiency of the entire computer system.
However, write buffer 22 does not improve the efficiency of reading the video memory 12. To improve the efficiency of CPU 10 reading data from video memory 12, the prior art includes a cache memory and controller 24. As shown in FIG. 3, cache memory and controller 24 is located in controller 20, and coupled between CPU 10 and video memory 12. Cache memory 24 is used to store blocks that have been retrieved from video memory 12. Cache memory 24 reads the data from video memory 12 during the cycle time allocated to CPU 10. However, once the data has been stored in cache memory 24, CPU 10 may read the data from cache memory 24 at any time, even during the time slot allocated for VDCU 14 to access video memory 12.
If CPU 10 attempts to read the data at a particular address in video memory 12, the data must be transferred to cache memory 24 unless the data is already stored in cache memory 24. If the data of the particular address is not in cache memory 24 (a "miss"), cache controller 24 reads the data at the particular address and the data at several successive addresses, and stores this block of data in cache memory 24. If the desired data is stored in cache memory 24 (a "hit"), the data can be sent from cache memory 24 to CPU 10 even though CPU 10 is in a cycle time allotted to the VDCU 14. Therefore, the efficiency of CPU 10 in reading video memory 12 is improved with the addition of cache memory and controller 24.
FIG. 4 illustrates a timing diagram for a video system using cache memory 24 shown in FIG. 3. The timing diagram shows two memory read cycles initiated by CPU 10. The first cycle illustrates a "miss," and the second cycle illustrates a "hit." When the MISS signal is high, it indicates that the data to be read is not in cache memory 24, and when the MISS signal is low it indicates that the data to be read is stored in cache memory 24. A READY signal tells CPU 10 when the data can be read from cache 24. Only when the READY signal is high can CPU 10 complete the memory read cycle by pulling the MEMORY READ signal high. The Row Address Strobe (RAS) and Column Address Strobe (CAS) signals are both output signals of controller 20, and are used to read the data in video memory 12 as will be understood by those skilled in the art. As shown in FIG. 4, CPU 10 reads DATA 1 directly from video memory 12 during the time period allocated to CPU 10, whereas DATA 2 is read from cache memory 24 outside of the allocated time period and in a much shorter time.
One problem with cache memory 24 is that if the occurrences of a "miss" are frequent, then the use of cache memory 24 becomes inefficient. The inefficiency results because not only the data of the particular address of interest, but also the data at several successive addresses must also be read from video memory 12 and stored in cache memory 24. The process of reading in extra data not only wastes time, but also occupies space in the cache static memory that may be used for other operations. Another problem with cache memory 24 is the hardware cost. The cache memory 24 comprises several groups of Static Random Access Memory (SRAM) together with cache control device that can be relatively expensive. Furthermore, the extra data read and stored by cache memory 24 is often unused in the standard process for generating images on display device 16.
Therefore, there is a need for a system and method for improving the efficiency in reading video memory without the hardware costs and the shortcomings of the prior art.